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information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9830 ? analog devices, inc., one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: features +5 v power supply 50 mhz speed on-chip sine look-up table on-chip 10-bit dac parallel loading power-down option 72 db sfdr 250 mw power consumption 48-pin qfp applications dds tuning digital demodulation general description this dds device is a numerically controlled oscillator em- ploying a phase accumulator, a sine look-up table and a 10-bit d/a converter integrated on a single cmos chip. modulation capabilities are provided for phase modulation and frequency modulation. clock rates up to 50 mhz are supported. frequency accu- racy can be controlled to one part in 4 billion. modulation is effected by loading registers through the parallel micro- processor interface. a power-down pin allows external control of a power-down mode. the part is available in a 48-pin qfp package. functional block diagram reset sleep iout iout comp refin fs adjust refout agnd avdd dgnd dvdd mclk d0 fselect d15 wr a0 a1 a2 psel0 psel1 12 ad9830 on-board reference full scale control 10-bit dac sin rom phase accumulator (32-bit) mux mux freq0 reg freq1 reg phase0 reg phase1 reg phase2 reg phase3 reg parallel register transfer control mpu interface s rev. b
C2C ad9830Cspecifications 1 parameter ad9830a units test conditions/comments signal dac specifications resolution 10 bits update rate (f max ) 50 msps max i out full scale 20 ma max output compliance 1 v max dc accuracy integral nonlinearity 1 lsb typ differential nonlinearity 0.5 lsb typ dds specifications 2 dynamic specifications signal-to-noise ratio 50 db min f mclk = f max , f out = 2 mhz total harmonic distortion C53 dbc max f mclk = f max , f out = 2 mhz spurious free dynamic range (sfdr) 3 f mclk = 6.25 mhz, f out = 2.11 mhz narrow band ( 50 khz) C72 dbc min ( 200 khz) C68 dbc min wide band ( 2 mhz) C50 dbc min clock feedthrough C55 dbc typ wake up time 1 ms typ power-down option yes voltage reference internal reference @ +25 c 1.21 volts typ t min to t max 1.21 7% volts min/max refin input impedance 10 mw typ reference tc 100 ppm/ c typ refout impedance 300 w typ logic inputs v inh , input high voltage v dd C0.9 v min v inl , input low voltage 0.9 v max i inh , input current 10 m a max c in , input capacitance 10 pf max power supplies f out = 2 mhz avdd 4.75/5.25 v min/v max dvdd 4.75/5.25 v min/v max i aa 25 ma max i dd 6 + 0.5/mhz ma typ i aa + i dd 4 60 ma max low power sleep mode 5 0.25 ma typ 1 m w resistor tied between 1 ma max refout and agnd (v dd = +5 v 6 5%; agnd = dgnd = 0 v; t a = t min to t max ; refin = refout; r set = 1 k v ; r load = 51 v for iout and iout unless otherwise noted) notes 1 operating temperature range is as follows: a version: C40 c to +85 c. 2 all dynamic specifications are measured using iout. 100% production tested. 3 f mclk = 6.25 mhz, frequency word = 5671c71c hex, f out = 2.11 mhz. 4 measured with the digital inputs static and equal to 0 v or dvdd. 5 the low power sleep mode current is 2 ma typically when a 1 m w resistor is not tied from refout to agnd. the ad9830 is tested with a capacitive load of 50 pf. the part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenu- ated. for example, a 10 mhz output signal will be attenuated by 3 db when the load capacitance equals 250 pf. specifications subject to change without notice. full-scale control 10-bit dac sin rom on-board reference 12 refout refin fs adjust comp iout iout 51w 50pf 51w 50pf avdd r set 1kw 10nf 10nf figure 1. test circuit with which specifications are tested rev. b
ad9830 C3C timing characteristics limit at t min to t max parameter (a version) units test conditions/comments t 1 20 ns min mclk period t 2 8 ns min mclk high duration t 3 8 ns min mclk low duration t 4 1 8 ns min wr rising edge before mclk rising edge t 4a 1 8 ns min wr rising edge after mclk rising edge t 5 8 ns min wr pulse width t 6 t 1 ns min duration between consecutive wr pulses t 7 5 ns min data/address setup time t 8 3 ns min data/address hold time t 9 1 8 ns min fselect, psel0, psel1 setup time before mclk rising edge t 9a 1 8 ns min fselect, psel0, psel1 setup time after mclk rising edge t 10 t 1 ns min reset pulse duration notes 1 see pin description section. guaranteed by design, but not production tested. t 1 t 2 t 3 t 4a t 4 t 5 t 6 mclk wr figure 2. wr Cmclk relationship a0, a1, a2 data wr t 6 t 8 t 7 t 5 valid data valid data figure 3. writing to a phase/frequency register t 9 valid data valid data valid data t 9a t 10 mclk fselect psel0, psel1 reset figure 4. control timing (v dd = +5 v 6 5%; agnd = dgnd = 0 v, unless otherwise noted) rev. b
ad9830 C4C absolute maximum ratings* ( t a = +25 c unless otherwise noted) avdd to agnd . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v dvdd to dgnd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v avdd to dvdd . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . C0.3 v to +0.3 v digital i/o voltage to dgnd . . . . . C0.3 v to dvdd + 0.3 v analog i/o voltage to agnd . . . . . C0.3 v to avdd + 0.3 v operating temperature range industrial (a version) . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c maximum junction temperature . . . . . . . . . . . . . . . . +150 c qfp q ja thermal impedance . . . . . . . . . . . . . . . . . 75 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this device features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configuration 36 35 34 33 32 31 30 29 28 27 26 25 nc avdd fs adjust agnd nc agnd agnd nc 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd reset a0 a1 a2 db0 db1 db11 dgnd db15 db14 db13 db12 db10 refin refout sleep dvdd dvdd dgnd mclk nc = no connect wr dvdd fselect psel0 dgnd db2 db3 db4 db9 db8 db7 db6 comp ad9830 db5 psel1 dvdd avdd iout iout rev. b
ad9830 C5C pin description mnemonic function power supply avdd positive power supply for the analog section. a 0.1 m f capacitor should be connected between avdd and agnd. avdd has a value of +5 v 5%. agnd analog ground. dvdd positive power supply for the digital section. a 0.1 m f decoupling capacitor should be connected between dvdd and dgnd. dvdd has a value of +5 v 5%. dgnd digital ground. analog signal and reference iout, iout current output. this is a high impedance current source. a load resistor should be connected between iout and agnd. iout should be either tied directly to agnd or through an external load resistor to agnd. fs adjust full-scale adjust control. a resistor (r set ) is connected between this pin and agnd. this determines the mag- nitude of the full-scale dac current. the relationship between r set and the full-scale current is as follows: iout full-scale = 16 v refin /r set v refin = 1.21 v nominal , r set = 1 k w typical refin voltage reference input. the ad9830 can be used with either the on-board reference, which is available from pin refout, or an external reference. the reference to be used is connected to the refin pin. the ad9830 ac- cepts a reference of 1.21 v nominal. refout voltage reference output. the ad9830 has an on-board reference of value 1.21 v nominal. the reference is made available on the refout pin. this reference is used as the reference to the dac by connecting refout to refin. refout should be decoupled with a 10 nf capacitor to agnd. comp compensation pin. this is a compensation pin for the internal reference amplifier. a 10 nf decoupling ceramic capacitor should be connected between comp and avdd. digital interface and control mclk digital clock input. dds output frequencies are expressed as a binary fraction of the frequency of mclk. the output frequency accuracy and phase noise are determined by this clock. fselect frequency select input. fselect controls which frequency register, freq0 or freq1, is used in the phase ac- cumulator. fselect is sampled on the rising mclk edge. fselect needs to be in steady state when an mclk rising edge occurs. if fselect changes value when an mclk rising edge occurs, there is an uncertainty of one mclk cycle as to when control is transferred to the other frequency register. to avoid any uncertainty, a change on fselect should not coincide with an mclk rising edge. wr write, edge-triggered digital input. the wr pin is used when writing data to the ad9830. the data is loaded into the ad9830 on the rising edge of the wr pulse. this data is then loaded into the destination register on the mclk rising edge. the wr pulse rising edge should not coincide with the mclk rising edge as there will be an uncertainty of one mclk cycle regarding the loading of the destination register with the new data. the wr ris- ing edge should occur before an mclk rising edge. the data will then be transferred into the destination register on the mclk rising edge. alternatively, the wr rising edge can occur after the mclk rising edge and the desti- nation register will be loaded on the next mclk rising edge. d0Cd15 data bus, digital inputs for destination registers. a0Ca2 address digital inputs. these address bits are used to select the destination register to which the digital data is to be written. psel0, psel1 phase select input. the ad9830 has four phase registers. these registers can be used to alter the value being in- put to the sin rom. the contents of the phase register can be added to the phase accumulator output, the inputs psel0 and psel1 selecting the phase register to be used. like the fselect input, the ad9830 samples the psel0 and psel1 inputs on the mclk rising edge. therefore, these inputs should be in steady state at the mclk rising edge or, there is an uncertainty of one mclk cycle as to when control is transferred to the selected phase register. sleep low power control, active low digital input. sleep puts the ad9830 into a low power mode. internal clocks are disabled and the dacs current sources and refout are turned off. the ad9830 is re-enabled by taking sleep high. reset reset, active low digital input. reset resets the phase accumulator to zero which corresponds to an analog output of midscale. rev. b
ad9830 C6C terminology integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the endpoints of the transfer function are zero scale, a point 0.5 lsb below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 lsb above the last code transition (111 . . . 10 to 111 . . . 11). the error is expressed in lsbs. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between two adjacent codes in the dac. signal to (noise + distortion) signal to (noise + distortion) is measured signal to noise at the output of the dac. the signal is the rms magnitude of the fun- damental. noise is the rms sum of all the nonfundamental sig- nals up to half the sampling frequency (f mclk /2) but excluding the dc component. signal to (noise + distortion) is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for a sine wave input is given by signal to ( noise + distortion ) = (6.02 n + 1.76) db where n is the number of bits. thus, for an ideal 10-bit con- verter, signal to (noise + distortion) = 61.96 db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad9830, thd is defined as thd = 20log ( v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonic. output compliance the output compliance refers to the maximum voltage which can be generated at the output of the dac to meet the specifi- cations. when voltages greater than that specified for the out- put compliance are generated, the ad9830 may not meet the specifications listed in the data sheet. for the ad9830, the maximum voltage which can be generated by the dac is 1v. spurious free dynamic range along with the frequency of interest, harmonics of the funda- mental frequency and images of the mclk frequency will be present at the output of a dds device. the spurious free dy- namic range (sfdr) refers to the largest spur or harmonic which is present in the band of interest. the wideband sfdr gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth 2 mhz about the fundamental frequency. the narrowband sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 200 khz and 50 khz about the fundamental frequency. clock feedthrough there will be feedthrough from the mclk input to the analog output. the clock feedthrough refers to the magnitude of the mclk signal relative to the fundamental frequency in the ad9830s output spectrum. rev. b
mclk frequency ?mhz total current ?ma 60 30 10 20 30 40 50 55 50 45 40 35 avdd = dvdd = +5v t a = +25 c f out = 200khz figure 5. typical current consumption vs. mclk frequency mclk frequency ?mhz sfdr ( 200khz) - db ?0 ?0 10 20 30 40 50 ?5 ?0 ?5 ?0 ?5 avdd = dvdd = +5v f out /f mclk = 1/3 figure 6. narrow band sfdr vs. mclk frequency mclk frequency ?mhz ?5 10 50 20 sfdr ( 2mhz) ?db 30 40 ?0 ?5 ?0 ?0 ?5 avdd = dvdd = +5v f out /f mclk = 1/3 figure 7. wide band sfdr vs. mclk frequency f out /f mclk ?5 ?5 0 0.35 0.05 0.1 0.15 0.2 0.25 0.3 ?0 ?5 ?0 ?5 ?0 avdd = dvdd = +5v 50mhz 30mhz 10mhz sfdr (0?clk/2) ?db figure 8. wb sfdr vs. f out /f mclk for various mclk frequencies snr ?db mclk frequency ?mhz 60 55 40 10 50 20 30 40 50 45 avdd = dvdd = +5v f out = f mclk /3 figure 9. snr vs. mclk frequency f out /f mclk 60 55 40 0 0.4 0.1 0.2 0.3 50 45 snr ?db 10mhz 30mhz 50mhz avdd = dvdd = +5v figure 10. snr vs. f out /f mclk for various mclk frequencies typical performance characteristicsCad9830 C7C rev. b
ad9830 C8C rbw 1khz vbw 3khz st 50 sec 10db/div 0 ?0 ?0 start 0hz stop 25mhz ?0 ?0 ?0 ?0 ?0 ?0 ?0 figure 14. f mclk = 50 mhz, f out = 9.1 mhz, frequency word = 2e978d50 rbw 1khz vbw 3khz st 50 sec 10db/div 0 ?0 ?0 start 0hz stop 25mhz ?0 ?0 ?0 ?0 ?0 ?0 ?0 figure 15. f mclk = 50 mhz, f out = 11.1 mhz, frequency word = 38d4fdf4 rbw 1khz vbw 3khz st 50 sec 10db/div 0 ?0 ?0 start 0hz stop 25mhz ?0 ?0 ?0 ?0 ?0 ?0 ?0 figure 16. f mclk = 50 mhz, f out = 13.1 mhz, frequency word = 43126e98 rbw 1khz vbw 3khz st 50 sec 10db/div 0 ?0 ?0 start 0hz stop 25mhz ?0 ?0 ?0 ?0 ?0 ?0 ?0 figure 11. f mclk = 50 mhz, f out = 2.1 mhz, frequency word = aco8312 rbw 1khz vbw 3khz st 50 sec 10db/div 0 ?0 ?0 start 0hz stop 25mhz ?0 ?0 ?0 ?0 ?0 ?0 ?0 figure 12. f mclk = 50 mhz, f out = 3.1 mhz, frequency word = fdf3b64 rbw 1khz vbw 3khz st 50 sec 10db/div 0 ?0 ?0 start 0hz stop 25mhz ?0 ?0 ?0 ?0 ?0 ?0 ?0 figure 13. f mclk = 50 mhz, f out = 7.1 mhz, frequency word = 245a1cac rev. b
ad9830 C9C rbw 1khz vbw 3khz st 50 sec 10db/div 0 ?0 ?0 start 0hz stop 25mhz ?0 ?0 ?0 ?0 ?0 ?0 ?0 figure 17. f mclk = 50 mhz, f out = 16.5 mhz, frequency word = 547ae148 register size description freq0 reg 32 bits frequency register 0. this defines the output frequency, when fselect = 0, as a fraction of the mclk frequency. freq1 reg 32 bits frequency register 1. this de- fines the output frequency, when fselect = 1, as a fraction of the mclk frequency. phase0 reg 12 bits phase offset register 0. when psel0 = psel1 = 0, the contents of this register are added to the out- put of the phase accumulator. phase1 reg 12 bits phase offset register 1. when psel0 = 1 and psel1 = 0, the contents of this register are added to the output of the phase accumulator. phase2 reg 12 bits phase offset register 2. when psel0 = 0 and psel1 = 1, the contents of this register are added to the output of the phase accumulator. phase3 reg 12 bits phase offset register 3. when psel0 = psel1 = 1, the contents of this register are added to the out- put of the phase accumula tor. figure 18. ad9830 control registers a2 a1 a0 destination register 0 0 0 freq0 reg 16 lsbs 0 0 1 freq0 reg 16 msbs 0 1 0 freq1 reg 16 lsbs 0 1 1 freq1 reg 16 msbs 1 0 0 phase0 reg 1 0 1 phase1 reg 1 1 0 phase2 reg 1 1 1 phase3 reg figure 19. addressing the control registers d15 d0 msb lsb figure 20. frequency register bits d15 d14 d13 d12 d11 d0 x xxxmsb lsb x = don't care figure 21. phase register bits rev. b
ad9830 C10C circuit description the a d9830 provides an exciting new level of integration for the rf/communic ations system designer. the ad9830 combines the numerical controlled oscillator (nco), sine look-up table, frequency and phase modulators, and a digital-to-analog converter on a single integrated circuit. the internal circuitry of the ad9830 consists of three main sections. these are: numerical controlled oscillator (nco) + phase modulator sine look-up table digital-to-analog converter the ad9830 is a fully integrated direct digital synthesis (dds) chip. the chip requires one reference clock, two low precision resistors and eight decoupling capacitors to provide digitally created sine waves up to 25 mhz. in addition to the generation of this rf signal, the chip is fully capable of a broad range of simple and complex modulation schemes. these modulation schemes are fully implemented in the digital do- main allowing accurate and simple realization of complex modulation algorithms using dsp techniques. theory of operation sine waves are typically thought of in terms of their magnitude form a (t) = sin ( wt). however, these are nonlinear and not easy to generate except through piece wise construction. on the other hand, the angular information is linear in nature. that is, the phase angle rotates through a fixed angle for each unit of time. the angular rate depends on the frequency of the signal by the traditional rate of w = 2p f magnitude phase +1 0 ? 2 p 0 figure 22. sine wave knowing that the phase of a sine wave is linear and given a ref- erence interval (clock period), the phase rotation for that period can be determined. d phase = wd t solving for w w = d phase / d t = 2p f solving for f and substituting the reference clock frequency for the reference period (1/f mclk = d t) f = d phase f mclk /2 p the ad9830 builds the output based on this simple equation. a simple dds chip can implement this equation with three major subcircuits. numerical controlled oscillator + phase modulator this consists of two frequency select registers, a phase accumu- lator and four phase offset registers. the main component of the nco is a 32-bit phase accumulator which assembles the phase component of the output signal. continuous time signals have a phase range of 0 to 2 p . outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. the digital implementation is no different. the accumulator simply scales the range of phase numbers into a multibit digital word. the phase accumulator in the ad9830 is implemented with 32 bits. therefore, in the ad9830, 2 p = 2 32 . likewise, the d phase term is scaled into this range of numbers 0 < d phase < 2 32 C1. making these substitutions into the equation above f = d phase f mclk /2 32 where 0 < d phase < 2 32 with a clock signal of 50 mhz and a phase word of 051eb852 hex f = 51eb852 50 mhz/2 32 = 1.000000000931 mhz the input to the phase accumulator (i.e., the phase step) can be selected either from the freq0 register or freq1 register and this is controlled by the fselect pin. ncos inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. more com- plex frequency modulation schemes can be implemented by up- dating the contents of these registers. this facilitates complex frequency modulation schemes, such as gmsk. following the nco, a phase offset can be added to perform phase modulation using the 12-bit phase registers. the con- tents of this register are added to the most significant bits of the nco. the ad9830 has four phase registers. the resolution of the phase registers equals 2 p /4096. sine look-up table (lut) to make the output useful, the signal must be converted from phase information into a sinusoidal value. since phase informa- tion maps directly into amplitude, a rom lut converts the phase information into amplitude. to do this, the digital phase information is used to address a sine rom lut. although the nco contains a 32-bit phase accumulator, the output of the nco is truncated to 12 bits. using the full resolution of the phase accumulator is impractical and unnecessary as this would require a look-up table of 2 32 entries. it is necessary only to have sufficient phase resolution in the luts such that the dc error of the output waveform is domi- nated by the quantization error in the dac. this requires the look-up table to have two more bits of phase resolution than the 10-bit dac. digital-to-analog converter the ad9830 includes a high impedance current source 10-bit dac, capable of driving a wide range of loads at different speeds. full-scale output current can be adjusted, for optimum power and external load requirements, through the use of a single external resistor (r set ). the dac can be configured for single or differential ended op- eration. iout can be tied directly to agnd for single ended operation or through a load resistor to develop an output volt- age. the load resistor can be any value required, as long as the rev. b
ad9830 C11C full-scale voltage developed across it does not exceed the voltage compliance range. since full-scale current is controlled by r set , adjustments to r set can balance changes made to the load resistor. however, if the dac full-scale output current is significantly less than 20 ma, the linearity of the dac may degrade. dsp and mpu interfacing the ad9830 has a parallel interface, with 16 bits of data being loaded during each write cycle. the frequency or phase registers are loaded by asserting the wr signal. the destination register for the 16-bit data is selected using the address inputs a0, a1 and a2. the phase registers are 12 bits wide so, only the 12 lsbs need to be validthe 4 msbs of the 16 bit word do not have to contain valid data. data is loaded into the ad9830 by pulsing wr low, the data being latched into the ad9830 on the rising edge of wr . the values of inputs a0, a1 and a2 are also latched into the ad9830 on the wr rising edge. the appropriate register is up- dated on the next mclk rising edge. to ensure that the ad9830 contains valid data at the rising edge of mclk, the rising edge of the wr pulse should not coincide with the rising mclk edge. the wr pulse must occur several nanoseconds before the mclk rising edge. if the wr rising edge occurs at the mclk rising edge, there is an uncertainty of one mclk cycle regarding the loading of the destination registerthe desti- nation register may be loaded with the new data immediately or the destination register may be updated on the next mclk ris- ing edge. to avoid any uncertainty, the times listed in the speci- fications should be complied with. fselect, psel0 and psel1 are sampled on the mclk rising edge. again, these inputs should be valid when an mclk rising edge occurs as there will be an uncertainty of one mclk cycle introduced otherwise. when these inputs change value, there will be a pipeline delay before control is transferred to the selected registerthere will be a pipeline delay before the analog output is controlled by the selected register. similarly, there is a delay when a new word is written to a register. psel0, psel1, fselect and wr have latencies of six mclk cycles. the flow chart in figure 23 shows the operating routine for the ad9830. when the ad9830 is powered up, the part should be reset using reset . this will reset the phase accumulator to zero so that the analog output is at midscale. reset does not reset the phase and frequency registers. these registers will con- tain invalid data and, therefore, should be set to zero by the user. the registers to be used should be loaded, the analog output be- ing f mclk /2 32 freg where freg is the value contained in the selected frequency register. this signal will be phase shifted by an amount 2 p /4096 phasereg where phasereg is the value co ntained in the selected phase register. when fselect, psel0 and psel1 are programmed, there will be a pipeline de- lay of approximately 6 mclk cycles before the analog output reacts to the change on these inputs. reset data write freg<0, 1> = 0 phasereg<0, 1, 2, 3> = 0 data write freg<0> = f out 0/f mclk *2 32 freg<1> = f out 1/f mclk *2 32 phasereg<3:0> = delta phase<0, 1, 2, 3> select data sources set fselect set psel0, psel1 dac output v out = v refin *8*r out /r set* (1 + sin(2 p(freg*f mclk *t/2 32 + phasereg/2 12 ))) wait 6 mclk cycles change phase? change fout? change freg? yes change phasereg? change psel0, psel1 yes no no change fselect yes no yes no figure 23. flow chart for ad9830 initialization and operation rev. b
ad9830 C12C applications the ad9830 contains functions which make it suitable for modulation applications. the part can be used to perform simple modulation such as fsk. more complex modulation schemes such as gmsk and qpsk can also be implemented using the ad9830. in a fsk application, the two frequency reg- isters of the ad9830 are loaded with different values, one fre- quency will represent the space frequency while the other will represent the mark frequency. the digital data stream is fed to the fselect pin which will cause the ad9830 to modulate the carrier frequency between the two values. the ad9830 has four phase registers which enable the part to perform psk. with phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount which is related to the bit str eam being input to the modulat or. the presence of four shift registers eases the interaction ne eded between the dsp and the ad9830. the frequ ency and phase registers can be written to continuously, if required. the maximum update rate equals the frequency of the mclk. however, if a selected register is loaded with a new word, there will be a delay of 6 mclk cycles before the analog output will change accordingly. the ad9830 is also suitable for signal generator applications. with its low current consumption, the part is suitable for mobile applications in which it can be used as a local oscillator. figure 24 shows the interface between the ad9830 and ad6459 which is a down converter used on the receive side of mobile phones or basestations. bandpass filter ifip ifim mxop mxom midpoint bias generator bias circuit loip filter 51w 51w 10 bits r set 1kw ad9830 ad6459 pll 0 90 gain tc compensation irxp irxn fref fltr qrxp qrxn gain gref rfhi rflo vps1 vps2 prup com1 com2 0.1? antenna figure 24. ad9830 and ad6459 receiver circuit rev. b
ad9830 C13C grounding and layout the printed circuit board that houses the ad9830 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes which can be separated easily. a mini- mum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad9830 is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad9830. if the ad9830 is in a system where mul- tiple devices require agnd to dgnd connections, the con- nection should be made at one point only, a star ground point that should be established as close as possible to the ad9830. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad9830 to avoid noise coupling. the power supply lines to the ad9830 should use as large a track as is pos- sible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this will reduce the ef- fects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. good decoupling is important. the analog and digital supplies to the ad9830 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. all analog and digital supplies should be decoupled to agnd and dgnd respectively with 0.1 m f ceramic capacitors in parallel with 10 m f tantalum capacitors. to achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. in systems where a common supply is used to drive both the avdd and dvdd of the ad9830, it is reco mmended that the systems avdd supply be used. this supply should have the recom- mended analog supply decoupling between the avdd pins of the ad9830 and agnd and the recommended digital supply decoupling capacitors between the dvdd pins and dgnd. rev. b
ad9830 rev. b | page 14 of 16 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw se ating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 1. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9830astz ?40c to +85c 48-lead low prof ile quad flat package [lqfp] st-48 ad9830astz-reel ?40c to +85c 48-lead low pr ofile quad flat package [lqfp] st-48 1 z = rohs compliant part. revision history 11/11rev. a to rev. b changed title from cmos complete dds to direct digital synthesizer, waveform generator ................................................... 1 changed tqfp to lqfp throughout ............................................ 1 changes to general description section ....................................... 1 deleted ad9830 evaluation board section, using the ad9830 evaluation board section, prototyping area section, xo vs. external clock section, and power supply section .................... 13 deleted figure 25; renumbered sequentially ............................. 13 deleted figure 26 and components list section........................ 14 updated outline dimensions ........................................................ 14 changes to ordering guide ........................................................... 14
ad9830 rev. b | page 15 of 16 notes
ad9830 rev. b | page 16 of 16 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10308-0-1 1 /11(b)

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